While no one knows where the markets will be in six months, we deeply believe that we’ll need dramatically more compute capacity in six years. We’re on the hunt for startups that will make that compute more capable and more efficient. Because in the AI era, more is never enough. More capex. More fabs. More chips. More power. All to deliver more tokens. Yet, we still aren’t meeting the insatiable demand. The largest infrastructure buildout in history has turned into whack-a-mole, where every apparently cleared bottleneck exposes another set of opportunities.
At Primary, we began developing our compute thesis before ChatGPT’s release, when we wrote about the geopolitical risks of lacking a domestic semiconductor supply chain after the post-pandemic supply shocks. In January 2023, we argued in the WSJ that transformer models would create an opening for new, specialized chips. That spring, we led the seed round in Etched, and we’ve been focused on investing in this space ever since.
Our thesis is that there is alpha at seed for compute. Consensus says incumbents will rule the day on scale and know-how, and it’s easy for seed investors to agree and move on: the capital requirements, time to market, technical complexity, and thin bench of diligence partners make a seed bet daunting. We see it differently. The semis industry is incredible at hyper-optimization, but meeting demand now requires radical bets on reinvention... and a new generation of founders is rising to the call. The best ones balance first-principles and AI-native thinking. They have rebel ambition and a reverence for industry legends. They’re going to change, and eventually rule, the world.
Here is our call for startups.
1. Making more good chips: metrology for 3D systems
As chips go 3D and systems become more advanced, yield is the all-important number.
Metrology measures whether features far smaller than the eye can see have the right dimensions and alignment. Inspection finds the defects. Both were hard in 2D, harder at 2.5D, and now dies are stacked vertically and joined by microbumps, TSVs, and hybrid bonding. HBM previewed the challenge: every stack on a Blackwell is eight or twelve DRAM dies bonded through TSVs, and SK hynix’s HBM3 yield has been reported at 60–70%, against 90%+ for conventional DRAM.
Yield used to be a process-control problem solved with statistics and armies of engineers. Each node starts low and climbs. But every node adds variables (backside power, new materials, more steps), the defects are now buried inside the package, and the interactions that kill a chip are too subtle for humans to find.
KLA (~$200B market cap) owns inspection. Decades of microscopes, robotics, software, and process knowledge. An installed base that won’t be dislodged. Equipment that can run up to 20% of a fab’s capex. But 92% of its business is process control on 2D wafers. That’s the roadmap it will keep improving... and the one a 3D strategy would have to cannibalize.
We believe that fabs, although more complex and capital-intense, demand the same technology innovation coming to factories and industrial sites globally. The fab of the future is intelligent and self-healing.
We want to meet teams building tools that see buried defects at production speed, and software that turns multimodal inspection data into the reason a chip failed.
2. Materials for the new age
Every hard problem in this post comes back to a material.
The last 50 years of semiconductors ran on silicon, and it’s likely the next 50 won’t. Silicon earned its run: abundant, heat tolerant, with the right electrical properties, and easy to turn into a transistor. The industry built its fabs and supply chains around it.
Most logic and memory transistors are built in silicon. Surrounding them is a much larger stack of materials that makes the computation possible: copper carries power and data, dielectrics insulate signals from one another, substrates connect the chip to the rest of the system, adhesives hold the package together, and thermal materials pull heat away.
As we move towards densely packaged systems, the materials around silicon are no longer passive support. They determine how closely components can be packed, how quickly signals can travel, how much power can reach the transistors, and how much heat the package can survive.
Stacking more components makes the demands on these materials much harder. Different materials expand at different rates when heated, causing packages to bend, bonds to crack, and layers to separate. Taller stacks also create longer and more difficult paths for heat to escape. At the same time, smaller connections and faster signals leave less room for impurities, surface variation, or electrical loss. A limitation in an adhesive, dielectric, substrate, or thermal material can now determine how much compute can fit into a system.
Materials are at the core of every chip problem. Heat: stacked dies, a longer path out, hotter hotspots. Power: megawatt racks and 800-volt DC need switches silicon can’t make. Light: optical data movement is the escape from copper, but silicon is a terrible light emitter, lasers still come from III-V compounds like indium phosphide, and putting them on a silicon process at volume remains the wall in front of photonic compute.
The incumbents have the reliability data, the labs, and the fab relationships, and all of it ties them to the products that built them. Meanwhile AI is changing how materials get found: models search formulation space, simulation predicts behavior, automated labs synthesize and test. The opportunity is closing the loop from discovery to a qualified, high-volume process... and qualifying a material’s properties is the moat once you’re through it. That’s the bet we made with Matterstack.
We want to meet founders who see materials as a full-stack problem, from discovery to manufacturing to productizing.
3. Cooling moves inside the chip
Cooling is becoming all the more pressing because a chip’s ability to cool itself is directly tied to its ability to run fast.
Compute is heat. The electricity that switches transistors ends up as thermal energy, and a chip that sheds more heat runs faster. Today’s cold plates sit on top of a package, so heat travels from the transistor through silicon, packaging, thermal interfaces, and a lid before it touches coolant. As we stack dies, that path just gets longer. Heat is also generated unevenly, creating hotspots that a plate on the lid can only cool indirectly.
Microfluidics takes the wall down: channels etched into the silicon, the lid, or the substrate, with coolant flowing beside the hottest transistors. Recent research has shown the path to performant microfluidic systems. The physics is proven. The manufacturable, serviceable, qualified version doesn’t exist.
That makes this a packaging step, not a cooling product. The customer is likely TSMC, Intel, and the OSATs, likely not the data center operator. The customer may also be the thermals lead, unable to meet rising cooling complexity with Ansys and other physics-based design and modeling tools. The incumbent is the foundries integrating this themselves down the line. Foundries integrate what exists rather than invent what doesn’t. Whoever shows up with a qualified microfluidic layer gets designed in across every customer the foundry serves... the way CoWoS went from a small product to a real inhibitor to advanced semis progress.
We want to meet the team that makes heat removal part of the package.
4. Power delivery, from the grid to a transistor
Racks are going from 10–20 kilowatts to a megawatt. The GPU core packed deep inside the system only needs a single volt. The delta presents an opportunity for efficiency.
Electricity enters the data center at high voltage and gets converted at the transformer, the switchgear, the row, the rack, and again inside the server on the way down to that volt. Every step loses energy. Power is voltage times current, so when rack power rises fifty-fold you either raise the voltage or run fifty times the current through the copper and lose far more to heat. That’s why the industry is moving to 800-volt DC: convert once at the facility, carry high-voltage DC to the rack, cut the steps, the copper, and the rack space that power equipment eats.
The rack layer belongs to Vertiv, Schneider, and Eaton, and they’ll likely sell 800V the way they sold 48V. The chip layer belongs to the power-semi majors (Infineon, TI, Navitas), selling silicon and GaN parts into a reference design. There are still parts to be accounted for: the converters, connectors, and delivery stages inside the package, where fabs are now burying power lines beneath the transistors (backside power delivery) because there’s no room beside them. There’s efficiency to be gained across the whole power path, especially when you aim to vertically integrate beyond your wedge.
We believe the solution is both a materials problem (see above) and a new stack waiting to form. GaN and SiC switch faster and hold more voltage than silicon; they’ve already taken the charger and the EV. The data center is next, and the company that owns high-ratio, high-density conversion at the package becomes the standard part in every rack. Efficiency has never carried this much premium.
We want to meet teams building the power stack around the chip.
5. Software for the flow of tokens
Qwen, DeepSeek, Kimi, and NVIDIA now ship two to three major open-weight models a month, up about 20% from a year ago.
The hardware underneath is fragmenting across GPU generations, custom accelerators, and edge chips. Every pairing of a new model and a new chip is a fresh optimization problem, and nothing between the weights and the silicon solves it automatically.
Compute is consumed as tokens, and the economics of a token are software decisions: which kernels run the model, how it’s split across chips, how prefill and decode are batched and scheduled, which hardware serves which request. Today those decisions are hand-tuned by the inference providers, who get a few hours’ notice from the labs and race to be first to serve. Those hours are their business. A new attention variant or a point release means tuning again.
NVIDIA owns the optimization layer for its own silicon and has no reason to make anyone else’s fast. The inference providers (Together, Fireworks, Baseten) own the day-zero race and have no reason to hand their edge to a competitor. The open-source runtimes, vLLM and SGLang, have made some strides capturing value through enterprise offerings, but the libraries remain neutral optimization tools. The gap is a solution that takes any model and compiles, partitions, and verifies it onto any hardware, then routes each token to the cheapest silicon that can produce it correctly.
Yes, this isn’t traditional semis. It’s representative of our view of compute as a supply chain that ends in a token... and the software that moves tokens through it is where a lot of the margin will sit.
We want to meet teams building the compiler and the router for tokens.
6. A new memory layer for agents
A single request, even on a small model, could tie up tens of gigabytes of KV cache, a meaningful fraction of one GPU’s HBM.
An agent is responsible for holding that while it executes. As we move to swarms and coordinated, long-running agents, that memory will be held for hours, days, even months on end.
When a transformer generates a token, it needs the keys and values from every token before it. Recomputing them each step would be prohibitive, so they’re cached, and the cache grows with the conversation and gets read on every step. Agents make every dimension worse: longer runs, more of them, swarms, and architectures that lean on the cache harder.
The industry has been fast to work on fixes, which are more like patches than full-stack memory solutions. PagedAttention uses GPU memory better, compression shrinks the cache, tiering moves cold state out of HBM. DeepSeek’s KVCache Storage in DeepInfer shows where it’s going: parts of the cache in a dedicated distributed store, retained for days, reused across requests. The cache is becoming a tier of infrastructure, like a database.
Everyone with a serving stack is building a piece of it: NVIDIA in Dynamo and TensorRT-LLM, vLLM, the model labs, the hyperscalers. Each piece is tied to its owner’s stack, which is why none of them will build the whole thing.
The whole thing is a memory layer for AI: hardware and software that decide what an agent keeps, compresses, moves, or recomputes, and move that state across chips and servers. Neutral across models, hardware, and runtimes, or it’s a feature. The more persistent agents get, the more that layer is worth.
We want to meet teams building the storage tier for agent state.
7. Storing AI’s data trail
The data trail of a training run is bigger than the run, and nobody deletes it.
A model starts with a training set and sheds checkpoints, fine-tunes, logs, synthetic data, and outputs along the way. For a video, voice, or image model, add bigger files of video, audio, and sensor streams. When the run ends, the resulting data isn’t immediately needed, but it can’t be deleted either, as it might train the next model, reproduce a result, or answer an audit. So it stays. HBM gets the attention. The opportunity is lower in the hierarchy.
Cold data lands on hard drives and tape. Drives spin whether anyone reads them, burning power and space until they’re replaced. Tape sips power at rest but needs robotic libraries and a physical wind to read, and every archive migrates as media ages. The drive duopoly (Seagate, Western Digital) and a few storage tape manufacturers have optimized this hierarchy for thirty years. But the strain of AI’s massive data problem opens this market to new technology.
Glass, ceramics, and optical substrates store data densely with no power and no migration. Microsoft’s Project Silica writes several terabytes into hundreds of layers inside a small piece of glass, with a projected life of at least 10,000 years. The medium is the start. The stack runs from the material through the write and read systems to the software that decides what goes to the archive and when.
The industry is creating data at an unprecedented rate. It has to keep it at the same pace.
We want to meet teams building the archive for the AI era.
8. A financial layer for compute
Compute is now a line item on every P&L. The capital markets haven’t caught up.
A startup that wants a cluster puts 20–40% down (and rising), then finances the rest of a bill that arrives after the capacity does. All of it before a dollar of revenue. The biggest labs play a different game: balance sheets, strategic partners, multi-year cloud commitments. Anthropic’s commitments could reportedly reach $750B. Everyone else competes for what’s left.
The supply side is getting financed fast. Neoclouds sign take-or-pay contracts and borrow against the contracts, the GPUs, and the buildings. CoreWeave closed an $8.5B facility in March against a single customer contract. NVIDIA is working with Apollo, BlackRock, Blackstone, Brookfield, Goldman, and KKR to mobilize $500B of third-party capital.
Two products need to exist. Financing for buyers: reservations financed, prepayments spread across a contract, underwriting on committed revenue, several buyers sharing a cluster’s risk. And liquidity for capacity already bought: usage fluctuates, architectures change, projects slip, newer chips arrive before contracts expire, and a market that resells or subleases what’s idle connects that stranded supply to buyers who need a month, not a year. All of this gets better as we get more granular about the data coming out of GPUs and how they perform.
The venture-scale version is bigger than either product. Compute becomes an asset class: standard ways to value it, depreciate it, and move its risk around, so lending markets can hold it the way they hold aircraft and real estate. The Venn diagram of compute and finance exploded in the last 12 months. The next year is about regulatory approvals, both sides of the market, and real volume.
We want to meet teams making compute legible to capital.